1. Field of the Invention
The present invention relates to a memory device mounted on a semiconductor device and a semiconductor device including the memory device. Specifically, the invention relates to a cache memory device having valid bits.
2. Description of the Related Art
Almost all the current central processing units (CPUs) are based on an architecture called the stored program system. According to this stored program system, instructions processed by a CPU and data necessary for the processing are stored in a memory, and the processing of the CPU is carried out by sequentially reading data from the memory.
However, this architecture has a problem in an access speed to the memory. As storing instructions processed by the CPU and data necessary for the processing, the memory is required to have a large capacity. It is difficult, however, to use a high access speed memory having a large capacity since a high access speed memory is expensive. Accordingly, it has been suggested that a low speed memory having a large capacity (hereinafter referred to as a main memory) is used in combination with a high speed memory having a small capacity (hereinafter referred to as a cache memory).
Operation using a main memory and a cache memory is described. First, a part of the data of the main memory, which is required for processing, is read and copied into the cache memory so that a CPU has access only to the cache memory in normal processing. If the data necessary for processing is not stored in the cache memory, the data of the main memory is read and copied into the cache memory, and the CPU has access thereto. In this case, processing takes time because of the copy from the main memory to the cache memory; however, high speed operation is enabled for the second time or later since the CPU has access only to the cache memory. Note that the case where required data is stored in the cache memory is called a cache hit, while the case where required data is not stored in the cache memory is called a cache miss.
A cache memory is collections of combinations of a tag memory and a data memory (hereinafter referred to as lines), and includes a memory portion that stores a valid bit corresponding to each line. The memory portion storing a valid bit stores whether data stored in each line is valid or not. The case where invalid data is stored in a line is, for example, immediately after a power supply is turned on, in which case the valid bits of all lines are required to be invalidated. This is because the cache memory, which is generally constituted by an SRAM (Static Random Access Memory), cannot hold data when a power supply is off, and thus data stored in the cache memory cannot be specified immediately after a power supply is turned on.
However, this invalidation of valid bits takes time since it is performed for each line. Accordingly, it is necessary to put a CPU in standby mode during the invalidation.
FIG. 6 is a timing chart showing an example of the conventional invalidation of valid bits. In FIG. 6, reference numeral 300 denotes a request signal for invalidation, 303 denotes a counter signal that is to be an address in invalidation, and 302 denotes a cache access signal from a CPU. When the request signal for invalidation 300 is issued at an event timing 400, valid bits are sequentially invalidated as the address of the cache access in invalidation while sequentially counting up the counter signal 303 for each clock cycle. The invalidation is completed when the counter value reaches the total number (n) of lines to be invalidated at an event timing 401. Then, a normal cache access starts in accordance with the cache access signal 302.
An example of such a technology is disclosed in Patent Document 1. That is to say, an access of a CPU to a cache memory is determined to be a cache miss without putting the CPU in standby mode during the invalidation of valid bits, so that the CPU has access to a main memory to read required data. After the invalidation is completed, the required data is immediately stored in a cache memory, which results in high speed operation of the cache memory.
[Patent Document 1] Japanese Patent Laid-Open No. 2005-44142
When a control circuit and a buffer are added to a cache memory as disclosed in Patent Document 1, miniaturization of the cache memory is prevented. In addition, the invalidation of valid bits is carried out for each line similarly to the conventional invalidation. This may increase processing time with an increase in the capacity of the cache memory, and thus the invalidation takes time of (the number of lines in the cache memory×one cycle) at maximum. Since the time for invalidation becomes dominant with an increase in the capacity of the cache memory, it is necessary to perform the invalidation at high speed in order to significantly reduce time.